1. Field of the Invention
The present invention relates to a CMOS image sensor, and more particularly, to a method of fabricating a CMOS image sensor. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for minimizing a dark current by minimizing a photodiode surface damage. The present invention is also suitable for reducing a contact resistance and a variation of the contact resistance of a read-out circuit within a unit pixel by uniformly forming salicide on an active area and on a gate electrode, except for a photodiode region.
2. Discussion of the Related Art
Generally, an image sensor is a semiconductor device that converts an optical image to an electric signal. Image sensors are mainly classified into a charge coupled device (CCD) and a CMOS (complementary metal oxide silicon) image sensor.
A general CCD has a complicated drive system, needs considerable power consumption, and requires a multi-step photo process. Hence, it is disadvantageous in that a process of fabricating the general CCD is complicated. Moreover, in the CCD, it is difficult to integrate a control circuit, a signal processing circuit, an analog/digital (A/D) converter, etc. on a CCD chip. Hence, it is difficult to reduce a size of the CCD. However, a CMOS image sensor has been given attention as a next generation image sensor that can overcome the disadvantages of the CCD.
In the CMOS image sensor, MOS transistors that correspond to the number of unit pixels are formed on a semiconductor substrate by CMOS technology using a control circuit, a signal processing circuit, etc. as peripheral circuits. Hence, the CMOS image sensor adopts a switching system that sequentially detects outputs of the unit pixels via the MOS transistors.
Using CMOS fabrication technology, the CMOS image sensor is advantageous as it requires low power consumption, has a simple fabricating process due to a small number of photo process steps. Since a control circuit, a signal processing circuit, an analog/digital (A/D) converter, etc. can be integrated on a CMOS image sensor chip, a reduced size of the CMOS image sensor may be facilitated. Hence, the CMOS image sensors are widely used in various application fields such as digital still cameras, digital video cameras, etc.
A related art CMOS image sensor is explained in detail with reference to FIG. 1 and FIG. 2 as follows. FIG. 1 is a layout of the unit pixel of a 4T type CMOS image sensor and FIG. 2 is a diagram of an equivalent circuit 100 of a unit pixel of the CMOS image sensor shown in FIG. 1.
Referring to FIG. 1, an active area 10 is defined in a unit pixel of a general 4T type CMOS image sensor. One photodiode (PD) 20 is formed on a wide region of the active area 10 and gate electrodes 110, 120, 130 and 140 of four transistors are overlapped with the rest of the active area 10. The gate electrode 110 configures a transfer transistor Tx. The gate electrode 120 configures a reset transistor Rx. The gate electrode 130 configures a drive transistor Dx. The gate electrode 140 configures a select transistor Sx.
The active area 10 of each of the transistors except the portion overlapped with the corresponding gate electrode 110, 120, 130 or 140, is doped with impurity ions to become source/drain regions of each of the transistors. Hence, a power source voltage Vdd is applied to the source/drain regions between the reset and drive transistors Rx and Dx, and a power source voltage Vss is applied to the source/drain region of the select transistor Sx. FIG. 2 shows an additional part FD of the equivalent circuit 100.
A method of fabricating a related art CMOS image sensor is explained with reference to FIGS. 3A to 3C as follows. FIGS. 3A to 3C are cross-sectional diagrams of the CMOS image sensor taken along a cutting line I-I′ shown in FIG. 1.
Referring to FIG. 3A, a lightly doped p type (p−) epitaxial layer 2 is formed on a p type semiconductor substrate 1. A trench is then formed by etching the epitaxial layer 2 in a device isolation area to a predetermined depth by photolithography using a mask defining an active area and the device isolation area. An oxide layer is formed on the epitaxial layer 2. Chemical mechanical polishing is performed on the oxide layer to fill the trench. Hence, a device isolation layer 3 is formed in the device isolation area.
A gate insulating layer 4 and a conductive layer are sequentially stacked over the substrate and are then selectively removed to form a gate insulating layer 4 and a gate electrode 5 on a transistor area. The conductive layer, and therefore the gate electrode 5, may be made of polysilicon.
Referring to FIG. 3B, a salicide blocking insulating layer 6 is deposited over the semiconductor substrate. A photoresist layer 7 is formed on the insulating layer 6. The photoresist layer 7 is patterned by exposure and development to cover a photodiode area. In particular, the photoresist pattern 7 covers the photodiode area and exposes a portion of the salicide blocking insulating layer 6 on the gate electrode 5. The exposed salicide blocking insulating layer 6 on the gate electrode 5 is selectively removed. The salicide blocking insulating layer 6 may be made of TEOS.
Referring to FIG. 3C, the photoresist pattern 7 is removed. Then, a salicide layer 8 is formed on an exposed surface of the gate electrode 5.
However, in the related art salicide forming method of the CMOS image sensor, a surface of the photodiode area is damaged by the etch process used to form the gate electrode from the conductive layer, or the etch process used to form a spacer from the insulating layer. The damage includes a crystalline defect generated from the photodiode surface. Hence, a dark current is generated.
Moreover, in the related art CMOS image sensor fabricating method, a salicide blocking mask is extended to prevent salicidation from occurring on the photodiode. Hence, salicide and no-salicide co-exist in the gate electrode and the active area configuring the read-out circuit of the pixel unit. This raises contact resistance. Further, an etching undercut of the salicide blocking insulating layer is inevitable due to the characteristics of a wet etch process. The undercut etch varies according to a location within a wafer. This variation changes contact resistance as well.